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NM27C128 131,072-Bit (16K x 8) High Performance CMOS EPROM
July 1998
NM27C128 131,072-Bit (16K x 8) High Performance CMOS EPROM
General Description
The NM27C128 is a high performance 128K UV Erasable Electrically Programmable Read Only Memory. It is manufactured with Fairchild's latest CMOS split gate EPROM technology which enables it to operate at speeds as fast as 90 ns access time over the full operating range. The NM27C128 provides microprocessor-based systems extensive storage capacity for large portions of operating system and application software. Its 90 ns access time provides high speed operation with high-performance CPUs. The NM27C128 offers a single chip solution for the code storage requirements of 100% firmware-based equipment. Frequently-used software routines are quickly executed from EPROM storage, greatly enhancing system utility. The NM27C128 is configured in the standard EPROM pinout which provides an easy upgrade path for systems which are currently using standard EPROMs. The NM27C128 is one member of a high density EPROM Family which range in densities up to 4 Mb.
Features
s High performance CMOS -- 90 ns access time s Fast turn-off for microprocessor compatibility s JEDEC standard pin configuration -- 28-pin PDIP package -- 32-pin chip carrier -- 28-pin CERDIP package s Drop-in replacement for 27C128 or 27128 s 40% faster programming time with Fairchild's turbo algorithm
Block Diagram
VCC GND VPP Data Outputs O0 - O7
OE PGM CE
Output Enable, and Chip Enable Logic
Output Buffers
..
Y Gating
Y Decoder
A0 - A14 Address Inputs 131,072-Bit Cell Matrix
.......
X Decoder
DS011329-1
(c) 1998 Fairchild Semiconductor Corporation
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NM27C128 131,072-Bit (16K x 8) High Performance CMOS EPROM
Connection Diagrams
27C080 27C040 27C020 27C010 27C512 27C256
A19 A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 O0 O1 O2 GND
VPP A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 O0 O1 O2 GND
VPP A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 O0 O1 O2 GND
VPP A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 O0 O1 O2 GND
DlP NM27C128
VPP A12 A7 A6 A5 A4 A3 A2 A1 A0 O0 O1 O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15
VCC PGM A13 A8 A9 A11 OE A10 CE O7 O6 O5 O4 O3
27C256
27C512 27C010 27C020
27C040 27C080
A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 O0 O1 O2 GND
VPP A12 A7 A6 A5 A4 A3 A2 A1 A0 O0 O1 O2 GND
VCC A14 A13 A8 A9 A11 OE A10 CE O7 O6 O5 O4 O3
VCC PGM VCC XX A14 A14 A13 A13 A8 A8 A9 A9 A11 A11 OE/VPP OE A10 A10 CE/PGM CE O7 O7 O6 O6 O5 O5 O4 O4 O3 O3
VCC PGM XX A14 A13 A8 A9 A11 OE A10 CE O7 O6 O5 O4 O3
VCC VCC A18 A18 A17 A17 A14 A14 A13 A13 A8 A8 A9 A9 A11 A11 OE OE/VPP A10 A10 CE/PGM CE/PGM O7 O7 O6 O6 O5 O5 O4 O4 O3 O3
DS011329-8
Note: Compatible EPROM pin configurations are shown in the blocks adjacent to the NM27C128 pins.
Commercial Temp. Range (0C to +70C) VCC = 5V 10%
Parameter/Order Number
NM27C128 Q, N, V 90 NM27C128 Q, N, V 120 NM27C128 Q, N, V 150 NM27C128 Q, N, V 200
Extended Temp. Range
CC
(-40C to +85C) V = 5V 10%
Parameter/Order Number
NM27C128 QE, NE, VE 120 NM27C128 QE, NE, VE 150 NM27C128 QE, NE, VE 200
Access Time (ns)
90 120 150 200
Access Time (ns)
120 150 200
Note: Surface mount PLCC package available for commercial and extended temperature ranges only.
Pin Names
Symbol
A0-A13 CE OE O0-O7 PGM NC
Package Types: NM27C128 Q, N, V XXX
Description
Addresses Chip Enable Output Enable Outputs Program No Connect
Q = Quartz-Windowed Ceramic DIP N = Plastic OTP DIP V = Surface-Mount PLCC * All packages conform to the JEDEC standard. * All versions are guaranteed to function for slower speeds.
PLCC
A7 A12 VPP NC VCC PGM A13
4 3 2 1 32 31 30
Top
A6 A5 A4 A3 A2 A1 A0 NC O0
5 6 7 8 9 10 11 12 13
14 15 16 17 18 19 20
29 28 27 26 25 24 23 22 21
A8 A9 A11 NC OE A10 CE O7 O6
O1 O2 GND NC O3 O4 O5
DS011329-3
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NM27C128 131,072-Bit (16K x 8) High Performance CMOS EPROM
Absolute Maximum Ratings (Note 1)
Storage Temperature All Input Voltages except A9 with Respect to Ground VPP and A9 with Respect to Ground VCC Supply Voltage with Respect to Ground ESD Protection -65C to +150C
All Output Voltages with Respect to Ground
VCC + 1.0V to GND -0.6V
Operating Range
-0.6V to +7V -0.7V to +14V -0.6V to +7V > 2000V
Range
Comm'l Industrial
Temperature
0C to +70C -40C to +85C
VCC
+5V 10% +5V 10%
Read Operation DC Electrical Characteristics Over Operating Range with VPP = VCC
Symbol
VIL VIH VOL VOH ISB1 ISB2 ICC1 IPP VPP ILI ILO
Parameter
Input Low Level Input High Level Output Low Voltage Output High Voltage VCC Standby Current (CMOS) VCC Standby Current (T2L) VCC Active Current, T2L Inputs VPP Supply Current VPP Read Voltage Input Load Current Output Leakage Current
Test Conditions
Min
-0.5 2.0
Max
0.8 VCC +1 0.4
Units
V V V V
IOL = 2.1 mA IOH = -2.5 mA CE = VCC 0.3V VIL = GND 0.3V, VIH = VCC 0.3V CE = VIH CE = OE = VIL, f = 5 MHz I/O = 0 mA VPP = VCC GND VIN = 5.5V or GND VOUT = 5.5V or GND -1 -10 3.5
100 1 35 10 VCC 1 10
A mA mA A V A A
AC Electrical Characteristics Over Operating Range with VPP = VCC
Symbol
tACC tCE tOE tCF (Note 2) tDF (Note 2) tOH (Note 2)
Parameter
Address to Output Delay CE to Output Delay OE to Output Delay CE High to Output Float OE High to Output Float Output Hold from Addresses, CE or OE, Whichever Occurred First
90 120 150 200 Units Min Max Min Max Min Max Min Max
90 90 50 30 35 120 120 50 30 35 150 150 50 45 45 200 200 50 55 55 ns ns ns ns ns
0
0
0
0
ns
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NM27C128 131,072-Bit (16K x 8) High Performance CMOS EPROM
Capacitance TA = +25C, f = 1 MHz (Note 2)
Symbol
CIN COUT
Parameter
Input Capacitance Output Capacitance
Conditions
VIN = 0V VOUT = 0V
Typ
6 9
Max
12 12
Units
pF pF
AC Test Conditions
Output Load 1 TTL Gate and CL = 100 pF (Note 8) 5 ns 0.45 to 2.4V Input Rise and Fall Times Input Pulse Levels
Timing Measurement Reference Level (Note 10) Inputs 0.8V and 2.0V Outputs 0.8V and 2.0V
AC Waveforms (Notes 6, 7, 9)
ADDRESSES
2V 0.8V
Addresses Valid
CE
2V 0.8V
t CF t CE t OE
(Note 3) (Notes 4, 5)
OE 0.8V t DF
(Notes 4, 5)
Valid Output
2V
OUTPUT
2V 0.8V
Hi-Z t ACC
(Note 3)
Hi-Z t OH
DS011329-4
Note 1: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note 2: This parameter is only sampled and is not 100% tested. Note 3: OE may be delayed up to tACC - tOE after the falling edge of CE without impacting tACC. Note 4: The tDF and tCF compare level is determined as follows: High to TRI-STATE(R), the measured VOH1 (DC) - 0.10V; Low to TRI-STATE, the measured VOL1 (DC) + 0.10V. Note 5: TRI-STATE may be attained using OE or CE . Note 6: The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1 F ceramic capacitor be used on every device between V CC and GND. Note 7: The outputs must be restricted to VCC + 1.0V to avoid latch-up and device damage. Note 8: TTL Gate: IOL = 1.6 mA, IOH = -400 A. CL = 100 pF includes fixture capacitance. Note 9: VPP may be connected to VCC except during programming. Note 10: Inputs and outputs can undershoot to -2.0V for 20 ns Max.
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NM27C128 131,072-Bit (16K x 8) High Performance CMOS EPROM
Programming Characteristics (Notes 11, 12, 13, 14)
Symbol
tAS tOES tCES tVPS tVCS tDS tAH tDH tDF tPW tOE IPP ICC TA VCC VPP tFR VIL VIH tIN tOUT OE Setup Time CE Setup Time VPP Setup Time VCC Setup Time Data Setup Time Address Hold Time Data Hold Time Output Enable to Output Float Delay Program Pulse Width Data Valid from OE VPP Supply Current during Programming Pulse VCC Supply Current Temperature Ambient Power Supply Voltage Programming Supply Voltage Input Rise, Fall Time Input Low Voltage Input High Voltage Input Timing Reference Voltage Output Timing Reference Voltage 2.4 0.8 0.8 20 6.25 12.5 5 0.0 4.0 2.0 2.0 0.45 25 6.5 12.75 CE = VIL CE = VIL CE = VIL OE = VIH
Parameter
Address Setup Time
Conditions
Min
1 1 1 1 1 1 0 1 0 45
Typ
Max
Units
s s s s s s s s
60 50 105 100 30 50 30 6.75 13.0
ns s ns mA mA C V V ns V V V V
Programming Waveforms (Note 13)
Program ADDRESS
2V 0.8V
Program Verify
Address N
t AS DATA
2V 0.8V
Data In Stable Add N
t AH Hi-Z
Data Out Valid Add N
t DS
t DH
t DF
6.0V
VCC
13.0V
tVCS
VPP
t VPS
CE
0.8V
t CES
2V 0.8V
PGM
t PW
2V
t OES
t OE
OE
0.8V
DS011329-5 Note 11: Fairchild's standard product warranty applies to devices programmed to specifications described herein. Note 12: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. The EPROM must not be inserted into or removed from a board with voltage applied to VPP or VCC. Note 13: The maximum absolute allowable voltage which may be applied to the VPP pin during programming is 14V. Care must be taken when switching the VPP supply to prevent any overshoot from exceeding this 14V maximum specification. At least a 0.1 F capacitor is required across VPP, VCC to GND to suppress spurious voltage transients which may damage the device. Note 14: During power up the PGM pin must be brought high ( VIH) either coincident with or before power is applied to VPP.
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NM27C128 131,072-Bit (16K x 8) High Performance CMOS EPROM
Turbo Programming Algorithm Flow Chart
VCC = 6.5V VPP = 12.75V n=0 ADDRESS = FIRST LOCATION
PROGRAM ONE 50s PULSE INCREMENT n
NO
DEVICE FAILED
YES
n = 10?
FAIL
VERIFY BYTE
PASS
LAST ADDRESS ?
YES
NO
INCREMENT ADDRESS n=0
ADDRESS = FIRST LOCATION
VERIFY BYTE INCREMENT ADDRESS
NO PASS
FAIL
PROGRAM ONE 50 s PULSE
LAST ADDRESS ?
YES
CHECK ALL BYTES 1ST: VCC = VPP = 6.0V 2ND: VCC = VPP = 4.3V
Note: The standard National Semiconductor algorithm may also be used but it will have longer programming time. DS011329-6
FIGURE 1.
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NM27C128 131,072-Bit (16K x 8) High Performance CMOS EPROM
Functional Description
DEVICE OPERATION
The six modes of operation of the EPROM are listed in Table 1. It should be noted that all inputs for the six modes are at TTL levels. The power supplies required are VCC and VPP. The VPP power supply must be at 12.75V during the three programming modes, and must be at 5V in the other three modes. The VCC power supply must be at 6.5V during the three programming modes, and at 5V in the other three modes.
Programming
CAUTION: Exceeding 14V on pin 1 (VPP) will damage the EPROM. Initially, and after each erasure, all bits of the EPROM are in the "1's" state. Data is introduced by selectively programming "0's" into the desired bit locations. Although only "0's" will be programmed, both "1's" and "0's" can be presented in the data word. The only way to change a "0" to a "1" is by ultraviolet light erasure. The EPROM is in the programming mode when the VPP power supply is at 12.75V, CE is at VIL, and OE is at VIH. It is required that at least a 0.1 F capacitor be placed across VPP, VCC to ground to suppress spurious voltage transients which may damage the device. The data to be programmed is applied 8 bits in parallel to the data output pins. The levels required for the address and data inputs are TTL. When the address and data are stable, an active low, TTL program pulse is applied to the PGM input. A program pulse must be applied at each address location to be programmed. The EPROM is programmed with the Turbo Programming Algorithm shown in Figure 1. Each Address is programmed with a series of 50 s pulses until it verifies good, up to a maximum of 10 pulses. Most memory cells will program with a single 50 s pulse. (The standard National Semiconductor algorithm may also be used but it will have longer programming time.) The EPROM must not be programmed with a DC signal applied to the PGM input. Programming multiple EPROM in parallel with the same data can be easily accomplished due to the simplicity of the programming requirments. Like inputs of the parallel EPROM may be connected together when they are programmed with the same data. A low level TTL pulse applied to the PGM input programs the paralleled EPROM.
Read Mode
The EPROM has two control functions, both of which must be logically active in order to obtain data at the outputs. Chip Enable (CE) is the power control and should be used for device selection. Output Enable (OE) is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that addresses are stable, address access time (tACC) is equal to the delay from CE to output (tCE). Data is available at the outputs tOE after the falling edge of OE, assuming that CE has been low and addresses have been stable for at least tACC -tOE.
Standby Mode
The EPROM has a standby mode which reduces the active power dissipation by over 99%, from 220 mW to 0.55 mW. The EPROM is placed in the standby mode by applying a CMOS high signal to the CE input. When in standby mode, the outputs are in a high impedance state, independent of the OE input.
Output Disable
The EPROM is placed in output disable by applying a TTL high signal to the OE input. When in output disable all circuitry is enabled, except the outputs are in a high impedance state (TRISTATE).
Output OR-Typing
Because the EPROM is usually used in larger memory arrays, Fairchild has provided a 2-line control function that accommodates this use of multiple memory connections. The 2-line control function allows for: 1. the lowest possible memory power dissipation, and 2. complete assurance that output bus contention will not occur. To most efficiently use these two control lines, it is recommended that CE be decoded and used as the primary device selecting function, while OE be made a common connection to all devices in the array and connected to the READ line from the system control bus. This assures that all deselected memory devices are in their low power standby modes and that the output pins are active only when data is desired from a particular memory device.
Program Inhibit
Programming multiple EPROMs in parallel with different data is also easily accomplished. Except for CE all like inputs (including OE) of the parallel EPROMs may be common. A TTL low level program pulse applied to an EPROM's CE input with VPP at 12.75V will program that EPROM. A TTL high level CE input inhibits the other EPROMs from being programmed.
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NM27C128 131,072-Bit (16K x 8) High Performance CMOS EPROM
Functional Description (Continued)
Program Verify
A verify should be performed on the programmed bits to determine whether they were correctly programmed. The verify may be performed with VPP at 12.75V. VPP must be at VCC, except during programming and program verify.
The EPROM should be placed within 1 inch of the lamp tubes during erasure. Some lamps have a filter on their tubes which should be removed before erasure. Table 1 shows the minimum EPROM erasure time for various light intensities. An erasure system should be calibrated periodically. The distance from lamp to device should be maintained at one inch. The erasure time increases as the square of the distance from the lamp (if distance is doubled the erasure time increases by factor of 4). Lamps lose intensity as they age. When a lamp is changed, the distance has changed, or the lamp has aged, the system should be checked to make certain full erasure is occurring. Incomplete erasure will cause symptoms that can be misleading. Programmers, components, and even system designs have been erroneously suspected when incomplete erasure was the problem.
AFTER PROGRAMMING
Opaque labels should be placed over the EPROM window to prevent unintentional erasure. Covering the window will also prevent temporary functional failure due to the generation of photo currents.
MANUFACTURER'S IDENTIFICATION CODE
The EPROM has a manufacturer's identification code to aid in programming. When the device is inserted in an EPROM programmer socket, the programmer reads the code and then automatically calls up the specific programming algorithm for the part. This automatic programming control is only possible with programmers which have the capability of reading the code. The Manufacturer's Identification code, shown in Table 2, specifically identifies the manufacture and device type. The code for NM27C128 is "8F83", where "8F" designates that it is made by Fairchild Semiconductor, and "83" designates a 128K part. The code is accessed by applying 12V 0.5V to address pin A9. Addresses A1-A8, A10-A13, and all control pins are held at VIL. Address pin A0 is held at VIL for the manufacturer's code, and held at VIH for the device code. The code is read on the eight data pins, O0 -O7 . Proper code access is only guaranteed at 25C to 5C.
SYSTEM CONSIDERATION
The power switching characteristics of EPROMs require careful decoupling of the devices. The supply current, ICC, has three segments that are of interest to the system designer: the standby current level, the active current level, and the transient current peaks that are produced by voltage transitions on input pins. The magnitude of these transient current peaks is dependent of the output capacitance loading of the device. The associated VCC transient voltage peaks can be suppressed by properly selected decoupling capacitors. It is recommended that at least a 0.1 F ceramic capacitor be used on every device between VCC and GND. This should be a high frequency capacitor of low inherent inductance. In addition, at least a 4.7 F bulk electrolytic capacitor should be used between VCC and GND for each eight devices. The bulk capacitor should be located near where the power supply is connected to the array. The purpose of the bulk capacitor is to overcome the voltage drop caused by the inductive effects of the PC board traces.
ERASURE CHARACTERISTICS
The erasure characteristics of the device are such that erasure begins to occur when exposed to light with wavelengths shorter than approximately 4000 Angstroms (A). It should be noted that sunlight and certain types of fluorescent lamps have wavelengths in the 3000A - 4000A range. The recommended erasure procedure for the EPROM is exposure to short wave ultraviolet light which has a wavelength of 2537A. The integrated dose (i.e., UV intensity x exposure time) for erasure should be a minimum of 15W-sec/cm2 .
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NM27C128 131,072-Bit (16K x 8) High Performance CMOS EPROM
Mode Selection
The modes of operation of NM27C128 listed in Table 1. A single 5V power supply is required in the read mode. All inputs are TTL levels except for VPP and A9 for device signature.
TABLE 1. Modes Selection Pins Mode
Read Output Disable Standby Programming Program Verify Program Inhibit
Note 15: X can be V IL or VIH.
CE
VIL X VIH VIL VIL VIH
OE
VIL VIH X VIH VIL X
PGM
VIH VIH X VIL VIH X
VPP
VCC VCC VCC 12.75V 12.75V 12.75V
VCC
5.0V 5.0V 5.0V 6.5V 6.5V 6.5V
Outputs
DOUT High-Z High-Z DIN DOUT High-Z
TABLE 2. Manufacturer's Identification Code Pins
Manufacturer Code Device Code
A0 (10)
VIL VIH
A9 (24)
12V 12V
O7 (19)
1 1
O6 (18)
0 0
O5 (17)
0 0
O4 (16)
0 0
O3 (15)
1 0
O2 (13)
1 0
O1 (12)
1 1
O0 (11)
1 1
Hex Data
8F 83
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NM27C128 131,072-Bit (16K x 8) High Performance CMOS EPROM
Physical Dimensions inches (millimeters) unless otherwise noted
28 1.465 (37.08) MAX 15
R 0.025 (0.64)
0.515 - 0.530 (13.08 - 13.46)
1 R 0.030-0.055 (0.76 - 1.40) TYP
0.280 0.010 (7.11 0.25) UV WINDOW
14
0.225 MAX TYP (5.72)
0.050-0.060 (1.27 - 1.52) TYP
Glass Sealant
0.180 (4.57) MAX
0.10 (2.54) MAX
0.590-0.620 (14.99 - (15.75)
0.125 (3.18) MIN TYP
0.090-0.110 0.015-0.021 (2.29 - 2.79) 0.060-0.100 (0.38 - 0.53) TYP 0.035 - 0.045 (1.52 - 2.54) TYP (0.76 - 1.14) TYP TYP
86-94 TYP
0.015 -0.060 (0.38 - 1.52) TYP
90 - 100 TYP
0.008-0.012 (0.20 - 0.25)TYP +0.025 (0.64) -0.060 (-1.523)
0.685 (17.40)
UV Window Cavity Dual-In-Line CerDIP Package (JQ) Order Number NM27C128QXXX Package Number J28CQ (C)
28 27 26 25 24 23 22 21 20 19 18 17 16 15
0.062 RAD TYP (1.575)
0.490 - 0.550 (12.446 - 13.97)
Pin #1 IDENT
123456 7
8 9 10 11 12 13 14
1.360 - 1.470 (34.544 - 37.34)
0.030 Max (0.762)
0.583 - 0.640 (14.81 - 16.26)
0.145 - 0.210 (3.683 - 5.334)
0.050 Typ (1.270) 0.125 - 0.165 (3.175-4.191) 0.015 Min (0.381)
90-105 0.580 MIN (14.73) 0.008 - 0.015 (0.203 - 0.381) 0.065 0.025 (1.65 0.635) 0.100 0.010 (2.54 --0.254) 0.018 0.003 (0.457 0.076) 86 94 Typ 0.120 - 0.150 (3.048 - 3.81)
0.035 - 0.070 (0.889 - 1.778)
28-Lead Plastic One-Time-Programmable Dual-In-Line Package Order Number NM27C128NXXX Package Number N28B
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NM27C128 131,072-Bit (16K x 8) High Performance CMOS EPROM
Physical Dimensions inches (millimeters) unless otherwise noted
0.485-0.495 [12.32-12.57] 0.007[0.18] S B D-E S 0.449-0.453 [11.40-11.51] -A0.045 [1.143] 0.000-0.010 [0.00-0.25] Polished Optional 4 5 0.549-0.553 [13.94-14.05] -B0.585-0.595 [14.86-15.11] 0.013-0.021 TYP [0.33-0.53] See detail A -J13 14 0.002[0.05] S A 0.007[0.18] S 0.007[0.18] S A F-G S -E20 21 0.007[0.18] M 0.078-0.095 [1.98-2.41] -C0.004[0.10] 0.020 [0.51] 0.005 Max [0.13] 0.0100 [0.254] C D-E, F-G S 0.106-0.112 [2.69-2.84] 0.023-0.029 [0.58-0.74] -HBase Plane
0.015 [0.38] Min Typ
0.007[0.18] S B D-E S 0.002[0.05] S B -D1 30 29 0.541-0.545 [13.74-13-84]
60
( [10.16] )
0.400
0.490-0530 [12.45-13.46] 0.015[0.38] S C D-E, F-G S
-G-
-F-
A F-G S
0.118-0.129 [3.00-3.28] 0.010[0.25] L B A D-E, F-G S B 0.042-0.048 45X [1.07-1.22]
B
0.026-0.032 Typ [0.66-0.81] 0.007[0.18] S H D-E, F-G S
, ,
0.025 [0.64] Min 0.006-0.012 [0.15-0.30] 0.019-0.025 [0.48-0.64]
0.050
0.123-0.140 [3.12-3.56]
0.045 [1.14] 0.025 [0.64] Min 0.021-0.027 [0.53-0.69]
Detail A Typical Rotated 90
R
0.030-0.040 [0.76-1.02]
0.065-0.071 [1.65-1.80]
0.053-0.059 [1.65-1.80] 0.031-0.037 [0.79-0.94] 0.027-0.033 [0.69-0.84]
Section B-B Typical
32-Lead Plastic Leaded Chip Carrier (PLCC) Order Number NM27C128VXXX Package Number VA32A
Life Support Policy
Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of Fairchild Semiconductor Corporation. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
Fairchild Semiconductor Americas Customer Response Center Tel. 1-888-522-5372 Fairchild Semiconductor Europe Fax: +44 (0) 1793-856858 Deutsch Tel: +49 (0) 8141-6102-0 English Tel: +44 (0) 1793-856856 Francais Tel: +33 (0) 1-6930-3696 Italiano Tel: +39 (0) 2-249111-1
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
Fairchild Semiconductor Hong Kong 8/F, Room 808, Empire Centre 68 Mody Road, Tsimshatsui East Kowloon. Hong Kong Tel; +852-2722-8338 Fax: +852-2722-8383
Fairchild Semiconductor Japan Ltd. 4F, Natsume Bldg. 2-18-6, Yushima, Bunkyo-ku Tokyo, 113-0034 Japan Tel: 81-3-3818-8840 Fax: 81-3-3818-8841
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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